1. Field of the Invention
The present invention relates to semiconductor magnetic-to-electric converters that measure the intensity of a magnetic field by means of Hall a effect device element and is particularly concerned with improvements in the dependency of their output characteristics on temperature.
2. Description of the Related Art
A Hall device is a device that produces a voltage proportional to the intensity of an applied magnetic field and is used as a sensing element that converts magnetic flux density to voltage. A Hall device and a signal processing circuit can be formed on a single semiconductor substrate, so that the resulting one-chip IC has been used as a semiconductor magnetic-to-electric converter.
FIG. 5 shows an exemplary circuit of a prior Hall IC. In FIG. 5, a Hall IC 1 comprises a Hall element 2, a differential amplifier that is composed of two NPN transistors Q1, Q2 and two resistors R1, R2 and performs differential amplification of an output voltage from Hall element 2, a constant-current circuit that comprises five NPN transistors Q3, Q4, Q8, Q10, Q11, four PNP transistors Q5, Q6, Q7, Q9, and two resistors R4, R5 and provides a constant current to the differential amplifier, and an amplifier that comprises two buffer circuits 12, 15, an operational amplifier 14, two NPN transistors Q17, Q18, and three resistors R13, R16, R19 and amplifies the output voltage of the differential amplifier to output the result.
Hall device 2 is mounted on a semiconductor substrate using an epitaxial layer and has input terminals 2a, 2b, through which an external power is supplied, and output terminals 2c, 2d, through which a voltage signal proportional to the intensity of a magnetic field is output. The base of NPN transistor Q1 is connected to output terminal 2c, and the base of NPN transistor Q2 is connected to output terminal 2d. An external regulated power supply, which is called external power supply hereafter, is applied to input terminal 2a to provide source voltage Vcc, and input terminal 2b is grounded.
The collector of NPN transistor Q1 is connected to the external power supply through resistor R1, which is a base-diffused resistor, and the collector of NPN transistor Q2 is connected to the external power supply through resistor R2, which is a base-diffused resistor. The emitters of NPN transistors Q1 and Q2 are connected to each other, and the connection is also connected to the collector of NPN transistor Q3. This NPN transistor Q3 and NPN transistor Q4 form a current mirror. The bases of NPN transistors Q3 and Q4 are connected to each other, and the connection is also connected to the collector of NPN transistor Q4. Further, the emitters of NPN transistors Q3 and Q4 are grounded.
The constant-current circuit that comprises PNP transistors Q5, Q6, Q7, Q9, NPN transistors Q8, Q10, Q11, resister R4, which is a base-diffused resister, and resister R5, which is a base-diffused resistor, provides a current source to the current mirror formed by NPN transistors Q3 and Q4. Also, PNP transistors Q5, Q6, Q7 form a current mirror, and NPN transistors Q10, Q11 form another current mirror. The emitters of PNP transistors Q5, Q6, Q7 and the collector of NPN transistor Q8 are connected to the external power supply. The bases of PNP transistors Q5, Q6, Q7 and NPN transistor Q8 are connected to each other, and the connection is connected to the emitter of NPN transistor Q9.
The emitter of NPN transistor Q8 is grounded through resistor R4, and the collector of PNP transistor Q9 is also grounded. The bases of NPN transistors Q10 and Q11 are connected to each other, and the connection is connected to the collector of NPN transistor Q10. Further, the emitter of NPN transistor Q10 is grounded, and the emitter of NPN transistor Q11 is grounded through resistor R5. The collector of PNP transistor Q5 is connected to the collector of NPN transistor Q10. The collector of PNP transistor Q6 is connected to the base of PNP transistor Q9, and the connection is connected to the collector of NPN transistor Q11.
The collector of PNP transistor Q7 is connected to the collector of NPN transistor Q4 and provides a current to the current mirror formed by NPN transistors Q3 and Q4. The connection between resistor R1 and the collector of NPN transistor Q1 is connected to the input terminal of buffer circuit 12, and the output terminal of buffer circuit 12 is connected to the-input terminal of operational amplifier 14 through resistor R13, which is a base-diffused resistor. The connection between resistor R2 and the collector of NPN transistor Q2 is connected to the input terminal of buffer circuit 15, and the output terminal of buffer circuit 15 is connected to the + input terminal of operational amplifier 14 through resistor R16, which is a base-diffused resistor.
The output terminal of operational amplifier 14 is connected to the bases of NPN transistors Q17 and Q18, and the collector of NPN transistor Q17 is connected to the + input terminal of operational amplifier 14. The collector of NPN transistor Q18 is connected to the connection between the output terminal of buffer circuit 12 and resistor 13. The emitters of NPN transistors Q17 and Q18 are connected to each other, and the connection is grounded through resistor R19, which is a resistor formed by using an epitaxial layer and called hereafter epi-resistor. The connection between the emitters of NPN transistors Q17, Q18, connected to resistor R19, is the output terminal of the Hall IC 1.
In the above circuitry, if a magnetic field is applied to Hall device 2, then a Hall voltage VH proportional to the intensity of the applied magnetic field occurs between the output terminals 2c and 2d of Hall device 2. The Hall voltage VH can be expressed by the following equation (1). ##EQU1## where VH is the Hall voltage, KH is the Hall coefficient, iH is the driving current for the Hall device, B is the magnetic flux density, d is the thickness of Hall device 2, fH is a coefficient depending on the shape of Hall device 2, Vcc is an applied voltage provided by the power supply, and Rin is an input resistance of Hall device 2.
A difference between collector currents ia and ib that respectively flow through NPN transistors Q1 and Q2 occurs based on the Hall voltage VH. Specifically, if a magnetic field is applied in such a way as an electric potential at output terminal 2c of Hall device 2 becomes higher than an electric potential at output terminal 2d of Hall device 2, then the collector current ia becomes greater than the collector current ib. Consequently, the voltage drop in resistor R1 becomes greater than the voltage drop in resistor R2, so that the input voltage of buffer circuit 15 becomes higher than the input voltage of buffer circuit 12, and hence the output voltage of buffer circuit 12 becomes lower than the output voltage of buffer circuit 15.
However, since the electric potentials at the two input terminals of operational amplifier 14 can be regarded as equal, a current ioa corresponding to the difference between the output voltages of buffer circuits 12 and 15 flows through resistor R16, which is located between buffer circuit 15 and the + input terminal of operational amplifier 14, in the direction such that a current flows into the collector of NPN transistor Q17. Further, since the input voltage at the + input terminal of operational amplifier 14 is greater than the input voltage at the - input terminal of operational amplifier 14, the electric potential at the output terminal of operational amplifier 14 becomes positive, and hence NPN transistor Q17 is set on, so that the current ioa flows into resistor R19 through NPN transistor Q17. At the same time, since NPN transistor Q18 is also set on, the current iob from buffer circuit 12 also flows into resistor R19 through NPN transistor Q18. The voltage generated in this way by the currents ioa and iob flowing into resistor R19 becomes an output voltage Vo of the Hall IC 1.
If the potential difference between the input terminals of buffer circuits 12 and 15 is .DELTA.V, then EQU ioa=.DELTA.V/R16, (2)
where R16 denotes the resistance value of resistor R16 as in subsequent equations.
The current ioa is the collector current of NPN transistor Q17, and the current iob is the collector current of NPN transistor Q18. NPN transistors Q17 and Q18 have the same current-amplification factor, and the values of their base currents are the same, since both currents are the same current output from operational amplifier 14. Therefore, ioa=iob.
The above ioa and iob are proportional to the above Hall voltage VH, so that if the proportional constant is .alpha., the above output voltage Vo becomes ##EQU2## where R19 denotes the resistance value of resistor R19 as in subsequent equations.
According to the above equations (1) and (3), the temperature characteristic of resistor R19 can be canceled out by the temperature characteristic of the input resistance Rin of Hall element 2, but the temperature characteristic of 1/R16 can not be compensated. Therefore, temperature compensation has not been sufficiently achieved for the Hall IC.